SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1137

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

• DTSEQ: Data Toggle Sequence
This field is set to indicate the PID of the current bank:
For IN transfers, it indicates the data toggle sequence that will be used for the next packet to be sent. This is not relative to
the current bank.
For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
By default, DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle
sequence should be Data0.
For High-bandwidth isochronous endpoint, a PEP_x interrupt is triggered if:
• SHORTPACKET: Short Packet Interrupt
This bit is set for non-control OUT endpoints, when a short packet has been received.
This triggers a PEP_x interrupt if UOTGHS_DEVEPTIMRx.SHORTPACKETE is one.
This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt.
• STALLEDI: STALLed Interrupt
This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by
writing a one to the STALLRQS bit). This triggers a PEP_x interrupt if STALLEDE is one.
This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.
• CRCERRI: CRC Error Interrupt
This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in
the bank as if no CRC error had occurred. This triggers a PEP_x interrupt if CRCERRE is one.
This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.
• OVERFI: Overflow Interrupt
This bit is set when an overflow error occurs. This triggers a PEP_x interrupt if OVERFE is one.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for
the packet. The packet is acknowledged and the UOTGHS_DEVEPTISRx.RXOUTI bit is set as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
• UOTGHS_DEVEPTIMRx.MDATAE is one and a MData packet has been received (DTSEQ=MData and
• UOTGHS_DEVEPTISRx.DATAXE is one and a Data0/1/2 packet has been received (DTSEQ=Data0/1/2 and
UOTGHS_DEVEPTISRx.RXOUTI is one).
UOTGHS_DEVEPTISRx.RXOUTI is one)
Value
0
1
2
3
MDATA
DATA0
DATA1
DATA2
Name
Description
Data0 toggle sequence
Data1 toggle sequence
Data2 toggle sequence (for high-bandwidth isochronous endpoint)
MData toggle sequence (for high-bandwidth isochronous endpoint)
SAM3X/A
SAM3X/A
1137
1137