SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 706

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

32.8.9
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
Note:
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0 = The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first
transfer and if the two transfers occur on the same Chip Select.
1 = The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after
the end of transfer for a minimal duration of:
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
706
706
–
–
31
23
15
7
SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans-
lated value unless the register is written.
DLYBCT
-----------------------
DLYBCT
-------------------------------- -
SAM3X/A
SAM3X/A
MCK
SPI Chip Select Register
MCK
(if DLYBCT field is different from 0)
+
1
30
22
14
SPI_CSRx[x=0..3]
0x40008030 (0), 0x4000C030 (1)
Read/Write
6
(if DLYBCT field equals 0)
BITS
29
21
13
5
28
20
12
4
DLYBCT
DLYBS
SCBR
”SPI Write Protection Mode
CSAAT
27
19
11
3
CSNAAT
26
18
10
2
Register”.
NCPHA
25
17
9
1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
CPOL
24
16
8
0