SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 454

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 26-22. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
26.14 External Wait
26.14.1
26.14.2
454
454
write2 controlling signal
read1 controlling signal
NBS0, NBS1,
SAM3X/A
SAM3X/A
Restriction
Frozen Mode
A0, A1
D[15:0]
A[23:2]
(NWE)
(NRD)
MCK
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be
set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00”
(disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT
signal delays the read or write operation in regards to the read or write controlling signal,
depending on the read and write modes of the corresponding chip select.
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle
for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Slow
Clock Mode
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
When the external device asserts the NWAIT signal (active low), and after internal synchroniza-
tion of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control
signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC
completes the access, resuming the access from the point where it was stopped. See
23. This mode must be selected when the external device uses the NWAIT signal to delay the
access and to freeze the SMC.
TDF_CYCLES = 5
read1 cycle
(“Slow Clock Mode” on page
read1 hold = 1
Read to Write
Wait State
TDF_CYCLES = 5
460).
4 TDF WAIT STATES
write2 setup = 1
(optimization disabled)
TDF_MODE = 0
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
write2 cycle
Figure 26-