SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1087

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

39.5.2.12
Figure 39-16. Example of an IN Endpoint with 1 Data Bank
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
UOTGHS_DEVEPTIMRx. FIFOCON
Overview
UOTGHS_DEVEPTISRx. TXINI
Management of IN Endpoints
The user has to consider that the byte counter is reset when a zero-length OUT packet is
received.
IN packets are sent by the USB device controller upon IN requests from the host. All data which
acknowledges or not the bank can be written when it is full.
The endpoint must be configured first.
T h e
UOTGHS_DEVEPTIMRx.FIFOCON when the current bank is free. This triggers a PEP_x inter-
rupt if the Transmitted IN Data Interrupt Enable (UOTGHS_DEVEPTIMRx.TXINE) bit is one.
UOTGHS_DEVEPTISRx.TXINI shall be cleared by software (by writing a one to the Transmitted
IN Data Interrupt Clear bit (UOTGHS_DEVEPTIDRx.TXINIC)) to acknowledge the interrupt,
what has no effect on the endpoint FIFO.
T h e u s e r t h e n w r i t e s i n t o t h e F I F O a n d w r i t e s a o n e t o t h e F I F O C o n t r o l C l e a r
(UOTGHS_DEVEPTIDRx.FIFOCONC) bit to clear the UOTGHS_DEVEPTIMRx.FIFOCON bit.
This allows the UOTGHS to send the data. If the IN endpoint is composed of multiple banks, this
a l s o s w i t c h e s t o t h e n e x t b a n k . T h e U O T G H S _ D E V E P T I S R x . T X I N I a n d
UOTGHS_DEVEPTIMRx.FIFOCON bits are updated in accordance with the status of the next
bank.
U O T G H S _ D E V E P T I S R x . T X I N I
UOTGHS_DEVEPTIMRx.FIFOCON.
The UOTGHS_DEVEPTISRx.RWALL bit is set when the current bank is not full, i.e. the software
can write further data into the FIFO.
SW
U O T G H S _ D E V E P T I S R x . T X I N I
write data to CPU
NAK
BANK 0
SW
IN
s h a l l
(bank 0)
DATA
b i t
a l w a y s
i s
HW
ACK
s e t
b e
c l e a r e d
a t
SW
write data to CPU
t h e
BANK 0
b e f o r e
s a m e
SAM3X/A
SAM3X/A
t i m e
c l e a r i n g
SW
IN
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