SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1090

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 39-19. Example of an OUT Endpoint with one Data Bank
Figure 39-20. Example of an OUT Endpoint with two Data Banks
1090
1090
Detailed description
UOTGHS_DEVEPTISRx. RXOUTI
UOTGHS_DEVEPTIMRx. FIFOCON
UOTGHS_DEVEPTISRx.RXOUTI
UOTGHS_DEVEPTIMRx.FIFOCON
OUT
SAM3X/A
SAM3X/A
OUT
(bank 0)
DATA
(bank 0)
DATA
The data is read, following the next flow:
If the endpoint uses several banks, the current one can be read while the following one is being
written by the host. Then, when the user clears UOTGHS_DEVEPTIMRx.FIFOCON, the follow-
ing bank may already be read and UOTGHS_DEVEPTISRx.RXOUTI is set immediately.
In Hi-Speed mode, the PING and NYET protocols are handled by the UOTGHS.
• When the bank is full, UOTGHS_DEVEPTISRx.RXOUTI and
• The user acknowledges the interrupt by writing a one to UOTGHS_DEVEPTICRx.RXOUTIC
• The user can read the byte count of the current bank from UOTGHS_DEVEPTISRx.BYCT to
• The user reads the data from the current bank by using the USBFIFOnDATA register, until all
• The user frees the bank and switches to the next bank (if any) by clearing
UOTGHS_DEVEPTIMRx.FIFOCON are set, which triggers a PEP_x interrupt if
UOTGHS_DEVEPTIMRx.RXOUTE is one.
in order to clear UOTGHS_DEVEPTISRx.RXOUTI.
know how many bytes to read, rather than polling UOTGHS_DEVEPTISRx.RWALL.
expected data frame is read or the bank is empty (in which case
UOTGHS_DEVEPTISRx.RWALL is cleared and UOTGHS_DEVEPTISRx.BYCT reaches
zero).
UOTGHS_DEVEPTIMRx.FIFOCON.
HW
ACK
ACK
HW
SW
read data from CPU
SW
BANK 0
OUT
NAK
read data from CPU
BANK 0
(bank 1)
DATA
SW
OUT
ACK
(bank 0)
DATA
HW
SW
HW
ACK
read data from CPU
SW
read data from CPU
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
BANK 1
SW
BANK 0