SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 948

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

37.11.1
37.11.2
37.12 HSMCI Transfer Done Timings
37.12.1
37.12.2
948
948
SAM3X/A
SAM3X/A
Boot Procedure, Processor Mode
Boot Procedure DMA Mode
Definition
Read Access
The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is
finished.
During a read access, the XFRDONE flag behaves as shown in
1. Configure the HSMCI data bus width programming SDCBUS Field in the
2. Set the byte count to 512 bytes and the block count to the desired number of blocks,
3. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register
4. The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the
5. Host processor can copy boot data sequentially as soon as the RXRDY flag is
6. When Data transfer is completed, host processor shall terminate the boot stream by
1. Configure the HSMCI data bus width by programming SDCBUS Field in the
2. Set the byte count to 512 bytes and the block count to the desired number of blocks by
3. Enable DMA transfer in the HSMCI_DMA register.
4. Configure DMA controller, program the total amount of data to be transferred and
5. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register
6. DMA controller copies the boot partition to the memory.
7. When DMA transfer is completed, host processor shall terminate the boot stream by
HSMCI_SDCR register. The BOOT_BUS_WIDTH field located in the device Extended
CSD register must be set accordingly.
writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.
with SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
BOOT_ACK field of the MMC device located in the Extended CSD register is set to one.
asserted.
writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
HSMCI_SDCR register. The BOOT_BUS_WIDTH field in the device Extended CSD
register must be set accordingly.
writing BLKLEN and BCNT fields of the HSMCI_BLKR Register.
enable the relevant channel.
with SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
writing the HSMCI_CMDR register with SPCMD field set to BOOTEND.
Figure
37-12.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12