SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1200

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

39.6.3.24
Name:
Address:
Access:
• CHANN_ENB: Channel Enable Command
0: DMA channel is disabled and no transfer will occur upon request. This bit is also cleared by hardware when the channel
source bus is disabled at the end of buffer.
If LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to set the corresponding CHANN_ENB bit
to start the described transfer, if needed.
If LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as
soon as both UOTGHS_HSTDMASTATUS.CHANN_ENB and CHANN_ACT flags read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then
UOTGHS_HSTDMASTATUS.CHANN_ENB bit is cleared.
If LDNXT_DSC bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs)
and the next descriptor is immediately loaded.
1: UOTGHS_HSTDMASTATUS.CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pending
request will start the transfer. This may be used to start or resume any requested transfer.
• LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command
0: no channel register is loaded after the end of the channel transfer.
1: th e cha nne l co ntro lle r load s t he ne xt de scripto r afte r t he en d of th e cur ren t tr an sfer, i.e. wh en th e
UOTGHS_HSTDMASTATUS.CHANN_ENB bit is reset.
If CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request.
DMA Channel Control Command Summary
1200
1200
BURST_LCK
Value
31
23
15
–
7
0
1
2
3
SAM3X/A
SAM3X/A
Host DMA Channel x Control Register
UOTGHS_HSTDMACONTROLx [x=1..7]
0x400AC718 [1], 0x400AC728 [2], 0x400AC738 [3], 0x400AC748 [4], 0x400AC758 [5], 0x400AC768 [6],
0x400AC778 [7]
Read-write
DESC_LD_IT
STOP_NOW
RUN_AND_STOP
LOAD_NEXT_DESC
RUN_AND_LINK
30
22
14
–
6
Name
END_BUFFIT
29
21
13
–
5
Stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
END_TR_IT
Description
28
20
12
–
4
BUFF_LENGTH
BUFF_LENGTH
END_B_EN
27
19
11
–
3
END_TR_EN
26
18
10
–
2
LDNXT_DSC
25
17
9
–
1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
CHANN_ENB
24
16
8
–
0