SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1223

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

40.8.3
40.8.3.1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Simple Receive Mailbox
CAN Controller Message Handling
Receive Handling
All interrupts are cleared by clearing the interrupt source except for the internal timer counter
overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the
CAN_SR register.
Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first
message received is stored in the mailbox data register. In Receive with Overwrite Mode, the
last message received is stored in the mailbox.
A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been config-
ured. Message ID and Message Acceptance Mask must be set before the Receive Mode is
enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically
cleared until the first message is received. When the first message has been accepted by the
mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set.
This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register.
Message data are stored in the mailbox data register until the software application notifies that
data processing has ended. This is done by asking for a new transfer command, setting the
MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal.
The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by
the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx
register. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents
from overwriting the first message by new ones while MRDY flag is set in the CAN_MSRx regis-
ter. See
– Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its
– Wake-up interrupt: This interrupt is generated after a wake-up and a bus
– Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all
– Internal timer counter overflow interrupt: This interrupt is generated when the
– Timestamp interrupt: This interrupt is generated after the reception or the
error counter value exceeds 96.
synchronization.
pending messages in transmission have been sent.
internal timer rolls over.
transmission of a start of frame or an end of frame. The value of the internal counter
is copied in the CAN_TIMESTP register.
Figure
40-11.
SAM3X/A
SAM3X/A
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