SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1092

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

39.5.2.17
39.5.2.18
39.5.2.19
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Global interrupts
Endpoint Interrupts
SAM3X/A
SAM3X/A
HB IsoFlush
CRC Error
Interrupts
This error only exists for high-bandwidth isochronous IN endpoints.
At the end of the micro-frame, if at least one packet has been sent to the host and there is a
missing IN token during this micro-frame, the bank(s) destined to this micro-frame is/are flushed
out to ensure a good data synchronization between the host and the device.
For instance, if NBTRANS is three (three transactions per micro-frame), if only the first IN token
(among 3) is well received by the UOTGHS, then the two last banks will be discarded.
This error only exists for isochronous OUT endpoints. It sets the CRC Error Interrupt
(UOTGHS_DEVEPTISRx.CRCERRI) bit, which triggers a PEP_x interrupt if the CRC Error
Interrupt Enable (UOTGHS_DEVEPTIMRx.CRCERRE) bit is one.
A CRC error can occur during the OUT stage if the UOTGHS detects a corrupted received
p a c k e t. T h e O U T p a c k e t i s s t o r e d i n t h e b a n k a s i f n o C R C e r r o r h a d o c c u r r e d
(UOTGHS_DEVEPTISRx.RXOUTI is set).
See the structure of the USB device interrupt system on
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
The processing device global interrupts are:
The exception device global interrupts are:
The processing device endpoint interrupts are:
• The Suspend (UOTGHS_DEVISR.SUSP) interrupt
• The Start of Frame (UOTGHS_DEVISR.SOF) interrupt with no frame number CRC error - the
• The Micro Start of Frame (UOTGHS_DEVISR.MSOF) interrupt with no CRC error.
• The End of Reset (UOTGHS_DEVISR.EORST) interrupt
• The Wake-Up (UOTGHS_DEVISR.WAKEUP) interrupt
• The End of Resume (UOTGHS_DEVISR.EORSM) interrupt
• The Upstream Resume (UOTGHS_DEVISR.UPRSM) interrupt
• The Endpoint x (UOTGHS_DEVISR.PEP_x) interrupt
• The DMA Channel x (UOTGHS_DEVISR.DMA_x) interrupt
• The Start of Frame (UOTGHS_DEVISR.SOF) interrupt with a frame number CRC error
• The Micro Start of Frame (UOTGHS_DEVFNUM.FNCERR.MSOF) interrupt with a CRC error
• The Transmitted IN Data Interrupt (UOTGHS_DEVEPTISRx.TXINI)
• The Received OUT Data Interrupt (UOTGHS_DEVEPTISRx.RXOUTI)
• The Received SETUP Interrupt (UOTGHS_DEVEPTISRx.RXSTPI)
• The Short Packet (UOTGHS_DEVEPTISRx.SHORTPACKET) interrupt
Frame Number CRC Error (UOTGHS_DEVFNUM.FNCERR) bit is zero.
(UOTGHS_DEVFNUM.FNCERR. is one)
Figure 39-6 on page
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
1074.