SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 229

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 13-4. User Reset State
13.4.4.4
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
periph_nreset
proc_nreset
(nrst_out)
RSTTYP
NRST
SLCK
NRST
MCK
Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These
commands are performed by writing the Control Register (RSTC_CR) with the following bits at
1:
The software reset is entered if at least one of these bits is set by the software. All these com-
mands can be performed independently or simultaneously. The software reset lasts 3 Slow
Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is
detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; syn-
chronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field
ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field
RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in
RSTTYP.
• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.
• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory
• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field
Resynch.
2 cycles
Any
Freq.
Any
system, and, in particular, the Remap Command. The Peripheral Reset is generally used for
debug purposes.
Except for debug purposes, PERRST must always be used in conjunction with PROCRST
(PERRST and PROCRST set both at 1 simultaneously).
ERSTL in the Mode Register (RSTC_MR).
>= EXTERNAL RESET LENGTH
Resynch.
2 cycles
XXX
Processor Startup
= 2 cycles
0x4 = User Reset
SAM3X/A
SAM3X/A
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