SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 457

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

26.14.3
Figure 26-25. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
internally synchronized
NBS0, NBS1,
NWAIT signal
Ready Mode
D[15:0]
NWAIT
A [23:2]
A0,A1
NWE
MCK
NCS
6
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins
the access by down counting the setup and pulse counters of the read/write controlling signal. In
the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
deassertion, the access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in
ure
26-26.
4
5
4
3
3
2
1
2
Write cycle
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
0
1
Wait STATE
0
1
Figure 26-25
0
1
0
and
Figure
SAM3X/A
SAM3X/A
26-26. After
Fig-
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