SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 350

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

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SAM3X/A
SAM3X/A
ority is linked to the channel number. The highest DMAC channel number has the highest
priority.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and
a destination peripheral on the same or different AMBA layer that occurs through the channel
FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to
the channel. If the destination peripheral is not memory, then a destination handshaking inter-
face is assigned to the channel. Source and destination handshaking interfaces can be assigned
dynamically by programming the channel registers.
Master interface: DMAC is a master on the AHB bus reading data from the source and writing it
to the destination over the AHB bus.
Slave interface: The APB interface over which the DMAC is programmed. The slave interface
in practice could be on the same layer as any of the master interfaces or on a separate layer.
Handshaking interface: A set of signal registers that conform to a protocol and handshake
between the DMAC and source or destination peripheral to control the transfer of a single or
chunk transfer between them. This interface is used to request, acknowledge, and control a
DMAC transaction. A channel can receive a request through one of two types of handshaking
interface: hardware or software.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or
chunk transfer between the DMAC and the source or destination peripheral.
Software handshaking interface: Uses software registers to control the transfer of a single or
chunk transfer between the DMAC and the source or destination peripheral. No special DMAC
handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing
an existing peripheral to the DMAC without modifying it.
Flow controller: The device (either the DMAC or source/destination peripheral) that determines
the length of and terminates a DMAC buffer transfer. If the length of a buffer is known before
enabling the channel, then the DMAC should be programmed as the flow controller. If the length
of a buffer is not known prior to enabling the channel, the source or destination peripheral needs
to terminate a buffer transfer. In this mode, the peripheral is the flow controller.
Transfer hierarchy:
buffer transfers, chunk or single, and AMBA transfers (single or burst) for non-memory peripher-
als.
Figure 23-3 on page 351
Figure 23-2 on page 351
shows the transfer hierarchy for memory.
illustrates the hierarchy between DMAC transfers,
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12