SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 86

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11.8.2.1
11.8.2.2
11.8.3
11.9
86
86
Instruction set summary
SAM3X/A
SAM3X/A
Power management programming hints
Wakeup from WFI or sleep-on-exit
Wakeup from WFE
Normally, the processor wakes up only when it detects an exception with sufficient priority to
cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor
wakes up, and before it executes an interrupt handler. To achieve this set the PRIMASK bit to 1
and the FAULTMASK bit to 0. If an interrupt arrives that is enabled and has a higher priority than
current exception priority, the processor wakes up but does not execute the interrupt handler
until the processor sets PRIMASK to zero. For more information about PRIMASK and FAULT-
MASK see
The processor wakes up if:
In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggers an
event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about the SCR see
page
ANSI C cannot directly generate the WFI and WFE instructions. The CMSIS provides the follow-
ing intrinsic functions for these instructions:
The processor implements a version of the Thumb instruction set.
ported instructions.
In
For more information on the instructions and operands, see the instruction descriptions.
Table 11-13. Cortex-M3 instructions
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
AND, ANDS
ASR, ASRS
• it detects an exception with sufficient priority to cause exception entry
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• most instructions can use an optional condition code suffix.
Table
void __WFE(void) // Wait for Event
void __WFE(void) // Wait for Interrupt
174.
11-13:
“Exception mask registers” on page
Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn, #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
Brief description
Add with Carry
Add
Add
Load PC-relative address
Logical AND
Arithmetic Shift Right
62.
“System Control Register” on
Table 11-13
Flags
N,Z,C,V
N,Z,C,V
N,Z,C,V
-
N,Z,C
N,Z,C
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
lists the sup-
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