SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 447

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

26.12.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
Figure 26-14. Early Read Wait State: Write with No Hold Followed by Read with No Setup
• if the write controlling signal has no hold time and the read controlling signal has no setup
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD =
time
signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode
26-15). The write operation must end with a NCS rising edge. Without an Early Read Wait
State, the write operation could not complete properly.
0), the feedback of the write control signal is used to control address, data, chip select and
byte select lines. If the external write control signal is not inactivated as expected due to load
capacitances, an Early Read Wait State is inserted and address, data and control signals are
maintained one more cycle. See
(Figure
NBS0, NBS1,
A0, A1
D[15:0]
A[23:2]
NWE
MCK
NRD
26-14).
write cycle
no hold
Figure
26-16.
Early Read
wait state
no setup
read cycle
SAM3X/A
SAM3X/A
(Figure
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