SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 347

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

23. AHB DMA Controller (DMAC)
23.1
23.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Description
Embedded Characteristics
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more AMBA buses. One channel is
required for each source/destination pair. In the most basic configuration, the DMAC has one
master interface and one channel. The master interface reads the data from a source and writes
it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also
known as a dual-access transfer.
The DMAC is programmed via the APB interface.
The DMAC embeds 6 channels:
Table 23-1.
DMAC Channel Number
• Programmable Arbitration Policy, Modified Round Robin and Fixed Priority are Available
• Acting as one Matrix Master
• Embeds 4 (SAM3A and 100-pin SAM3X) or 6 (144-pin and 217-pin SAM3X) channels
• Linked List support with Status Write Back operation at End of Transfer
• Word, HalfWord, Byte transfer support.
• Handles high speed transfer of SPI0-1, SSC and HSMCI (peripheral to memory, memory to
• Memory to memory transfer
32 bytes FIFO for Channel Buffering
8 bytes FIFO for Channel Buffering
peripheral)
DMA Channel Size
0
1
2
3
4
5
DMA Channels
FIFO Size
(Channels 0, 1 and 2)
100-pin SAM3X
(Channel 3)
32
32
8
8
8
8
SAM3A
3
1
(Channels 0, 1, 2 and 4)
(Channels 3 and 5)
144-pin SAM3X
217-pin SAM3X
4
2
SAM3X/A
SAM3X/A
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