SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 814

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

35.7.8.5
35.7.8.6
Figure 35-40. Header Transmission
814
814
Write RSTSTA=1
in US_CSR
in US_CSR
Baud Rate
US_LINIR
US_LINIR
in US_CR
TXRDY
LINBK
Clock
LINID
Write
TXD
SAM3X/A
SAM3X/A
Character Reception
Header Transmission (Master Node Configuration)
ID
See “Receiver Operations” on page 795.
All the LIN Frames start with a header which is sent by the master node and consists of a Synch
Break Field, Synch Field and Identifier Field.
So in Master node configuration, the frame handling starts with the sending of the header.
The header is transmitted as soon as the identifier is written in the LIN Identifier register
(US_LINIR). At this moment the flag TXRDY falls.
The Break Field, the Synch Field and the Identifier Field are sent automatically one after the
other.
The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the charac-
ter 0x55 and the Identifier corresponds to the character written in the LIN Identifier Register
(US_LINIR). The Identifier parity bits can be automatically computed and sent (see
35.7.8.9).
The flag TXRDY rises when the identifier character is transferred into the Shift Register of the
transmitter.
As soon as the Synch Break Field is transmitted, the flag LINBK in the Channel Status register
(US_CSR) is set to 1. Likewise, as soon as the Identifier Field is sent, the flag LINID in the Chan-
nel Status register (US_CSR) is set to 1. These flags are reset by writing the bit RSTSTA to 1 in
the Control register (US_CR).
13 dominant bits (at 0)
Break Field
1 recessive bit
Delimiter
Break
(at 1)
Start
Bit
1
0
Synch Byte = 0x55
1
0
1
0
1
0
Stop
Bit
Start
Bit
ID0
ID1
ID2
ID3
ID4
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
ID5
ID6
ID7
Stop
Bit
Section