SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1183

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

This bit is cleared when UOTGHS_HSTPIPICR.RXSTALLDIC bit is written to one.
• CRCERRI: CRC Error Interrupt
This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt
if UOTGHS_HSTPIPIMR.TXSTPE bit is one.
This bit is cleared when UOTGHS_HSTPIPICR.CRCERRIC bit is written to one.
• OVERFI: Overflow Interrupt
This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is
triggered if UOTGHS_HSTPIPIMR.OVERFIE bit is one.
This bit is cleared when UOTGHS_HSTPIPICR.OVERFIC bit is written to one.
• NAKEDI: NAKed Interrupt
This bit is set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if
UOTGHS_HSTPIPIMR.NAKEDE bit is one.
This bit is cleared when UOTGHS_HSTPIPICR.NAKEDIC bit written to one.
• PERRI: Pipe Error Interrupt
T h i s b i t i s s e t w h e n a n e r r o r o c c u r s o n t h e c u r r e n t b a n k o f t h e p i p e . T h i s t r i g g e r s a n i n t e r r u p t i f
UOTGHS_HSTPIPIMR.PERRE bit is set. Refer to the UOTGHS_HSTPIPERRx register to determine the source of the
error.
This bit is cleared when the error source bit is cleared.
• TXSTPI: Transmitted SETUP Interrupt
This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if
UOTGHS_HSTPIPIMR.TXSTPE bit is one.
This bit is cleared when UOTGHS_HSTPIPICR.TXSTPIC bit is written to one.
• UNDERFI: Underflow Interrupt
This bit is set, for isochronous and Interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the
UNDERFIE bit is one.
This bit is set, for Isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe. (The pipe
cannot send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) will be sent
instead.
This bit is set, for Isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe. i.e, the current
bank of the pipe is not free whereas a new IN USB packet is received. This packet is not stored in the bank. For Interrupt
pipe, the overflowed packet is ACKed to respect the USB standard.
This bit is cleared when UOTGHS_HSTPIPICR.UNDERFIEC bit is written to one.
• TXOUTI: Transmitted OUT Data Interrupt
T h i s b i t i s s e t w h e n t h e c u r r e n t O U T b a n k i s f r e e a n d c a n b e f i l l e d . T h i s t r i g g e r s a n i n t e r r u p t i f
UOTGHS_HSTPIPIMR.TXOUTE bit is one.
This bit is cleared when UOTGHS_HSTPIPICR.TXOUTIC bit is written to one.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
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