SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1081

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

39.5.2
39.5.2.1
39.5.2.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
USB Device Operation
Introduction
Power-On and Reset
The UOTGHS_SR.ID bit is effective whether the UOTGHS is enabled or not.
In device mode, the UOTGHS supports hi-, full- and low-speed data transfers.
In addition to the default control endpoint, 10 endpoints are provided, which can be configured
with an isochronous, bulk or interrupt type, as described in
As the device mode starts in Idle state, the pad consumption is reduced to the minimum.
Figure 39-12 on page 1081
Figure 39-12. Device Mode States
After a hardware reset, the UOTGHS device mode is in Reset state. In this state:
D + o r D - w i l l b e p u l l e d u p a c c o r d i n g t o t h e s e l e c t e d s p e e d a s s o o n a s t h e
UOTGHS_DEVCTRL.DETACH bit is written to zero and VBus is present. See
for further details.
When the UOTGHS is enabled (UOTGHS_CTRL.USBE is written to one) in device mode
(UOTGHS_SR.ID is one), its device mode state goes to the Idle state with minimal power con-
sumption. This does not require the USB clock to be activated.
The UOTGHS device mode can be disabled and reset at any time by disabling the UOTGHS (by
writing a zero to UOTGHS_CTRL.USBE) or when the host mode is engaged (UOTGHS_SR.ID
is zero).
• the macro clock is stopped to minimize the power consumption (UOTGHS_CTRL.FRZCLK is
• the internal registers of the device mode are reset,
• the endpoint banks are de-allocated,
• neither D+ nor D- is pulled up (UOTGHS_DEVCTRL.DETACH is written to one).
written to one),
UOTGHS_HSTCTRL.RESET
describes the UOTGHS device mode main states.
UOTGHS_CTRL.USBE = 0
HW
| UOTGHS_SR.ID = 0
Reset
UOTGHS_CTRL.USBE = 0
| UOTGHS_SR.ID = 0
UOTGHS_CTRL.USBE = 1
state>
other
<any
& UOTGHS_SR.ID = 1
Table 39-1 on page
Idle
SAM3X/A
SAM3X/A
1067.
“Device mode”
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