SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1138

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

• NAKINI: NAKed IN Interrupt
This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers a PEP_x
interrupt if NAKINE is one.
This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.
• HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the micro-frame, if less
than N transaction has been completed by the UOTGHS without underflow error. This may occur in case of a missing IN
token. In this case, the bank are flushed out to ensure the data synchronization between the host and the device. This trig-
gers a PEP_x interrupt if HBISOFLUSHE is one.
This bit is cleared when the HBISOFLUSHIC bit is written to one. This will acknowledge the interrupt.
• NAKOUTI: NAKed OUT Interrupt
This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers a PEP_x
interrupt if NAKOUTE is one.
This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.
• HBISOINERRI: High bandwidth isochronous IN Underflow Error Interrupt
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the microframe, if less
than N bank was written by the cpu within this micro-frame. This triggers a PEP_x interrupt if HBISOINERRE is one.
This bit is cleared when the HBISOINERRIC bit is written to one. This will acknowledge the interrupt.
• UNDERFI: Underflow Interrupt
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers a PEP_x interrupt if
UNDERFE is one.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then auto-
matically sent by the UOTGHS.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU
is not fast enough. The packet is lost.
Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
• RXSTPI: Received SETUP Interrupt
This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers a
PEP_x interrupt if RXSTPE is one.
Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT
endpoints.
• RXOUTI: Received OUT Data Interrupt
This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers
a PEP_x interrupt if UOTGHS_DEVEPTIMRx.RXOUTE is one.
Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free
the bank.
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11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12