SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 175

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11.21.8
• STKALIGN
Indicates stack alignment on exception entry:
0: 4-byte aligned
1: 8-byte aligned.
On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the excep-
tion it uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the
hard fault and FAULTMASK escalated handlers:
0: data bus faults caused by load and store instructions cause a lock-up
1: handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe sys-
tem devices and bridges to detect control path problems and fix them.
• DIV_0_TRP
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: do not trap divide by 0
1: trap divide by 0.
When this bit is set to 0,a divide by zero returns a quotient of 0.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
31
23
15
7
Configuration and Control Register
Reserved
30
22
14
6
The CCR controls entry to Thread mode and enables:
See the register summary in
The bit assignments are:
• the handlers for hard fault and faults escalated by FAULTMASK to ignore bus faults
• trapping of divide by zero and unaligned accesses
• access to the STIR by unprivileged software, see
page
162.
29
21
13
5
Reserved
DIV_0_TRP
28
20
12
4
Table 11-30 on page 165
Reserved
Reserved
UNALIGN_T
RP
27
19
11
3
“Software Trigger Interrupt Register” on
Reserved
for the CCR attributes.
26
18
10
2
USERSETM
STKALIGN
PEND
25
17
9
1
SAM3X/A
SAM3X/A
BFHFNMIGN
NONBASET
HRDENA
24
16
8
0
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