SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1202

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

39.6.3.25
Name:
Address:
Access:
• CHANN_ENB: Channel Enable Status
0 : i f c l e a r e d , t h e D M A c h a n n e l n o l o n g e r t r a n s f e r s d a t a , a n d m a y l o a d t h e n e x t d e s c r i p t o r i f
UOTGHS_HSTDMACONTROLx.LDNXT_DSC bit is set.
When any transfer is ended either due to an elapsed byte count or a UOTGHS device initiated transfer end, this bit is auto-
matically reset.
1: if set, the DMA channel is currently enabled and transfers data upon request.
This bit is normally set or cleared by writing into UOTGHS_HSTDMACONTROLx.CHANN_ENB bit field either by software
or descriptor loading.
If a channel request is currently serviced when UOTGHS_HSTDMACONTROLx.CHANN_ENB bit is cleared, the DMA
FIFO buffer is drained until it is empty, then this status bit is cleared.
• CHANN_ACT: Channel Active Status
0: the DMA channel is no longer trying to source the packet data.
When a packet transfer is ended this bit is automatically reset.
1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel.
When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor
load (if any) and potentially until UOTGHS packet transfer completion, if allowed by the new descriptor.
• END_TR_ST: End of Channel Transfer Status
0: cleared automatically when read by software.
1: set by hardware when the last packet transfer is complete, if the UOTGHS device has ended the transfer.
Valid until CHANN_ENB flag is cleared at the end of the next buffer transfer.
• END_BF_ST: End of Channel Buffer Status
0: cleared automatically when read by software.
1: set by hardware when BUFF_COUNT count-down reaches zero.
Valid until CHANN_ENB flag is cleared at the end of the next buffer transfer.
1202
1202
31
23
15
–
7
–
SAM3X/A
SAM3X/A
Host DMA Channel x Status Register
UOTGHS_HSTDMASTATUSx [x=1..7]
0x400AC71C [1], 0x400AC72C [2], 0x400AC73C [3], 0x400AC74C [4], 0x400AC75C [5], 0x400AC76C [6],
0x400AC77C [7]
Read-write
DESC_LDST
30
22
14
–
6
END_BF_ST
29
21
13
–
5
END_TR_ST
28
20
12
–
4
BUFF_COUNT
BUFF_COUNT
27
19
11
–
–
3
26
18
10
–
2
–
CHANN_ACT
25
17
9
–
1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
CHANN_ENB
24
16
8
–
0