SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1146

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

• MDATAE: MData Interrupt
This bit is set when UOTGHS_DEVEPTIERx.MDATAES bit is written to one. This will enable the Multiple DATA interrupt.
(see DTSEQ bits)
This bit is cleared when UOTGHS_DEVEPTIDRx.MDATAEC bit is written to one. This will disable the Multiple DATA
interrupt.
• SHORTPACKETE: Short Packet Interrupt
If this bit is set for non-control IN endpoints, a short packet transmission is guaranteed upon ending a DMA transfer, thus
signaling an end of isochronous frame or a bulk or interrupt end of transfer, provided that he End of DMA Buffer Output
Enable (END_B_EN) bit and the Automatic Switch (AUTOSW) bit are written to one.
This bit is set when UOTGHS_DEVEPTIERx.SHORTPACKETES bit is written to one. This will enable the Short Packet
interrupt (UOTGHS_DEVEPTISRx.SHORTPACKET).
This bit is cleared when UOTGHS_DEVEPTIDRx.SHORTPACKETEC bit is written to one. This will disable the Short
Packet interrupt (UOTGHS_DEVEPTISRx.SHORTPACKET).
• STALLEDE: STALLed Interrupt
This bit is set when UOTGHS_DEVEPTIERx.STALLEDES bit is written to one. This will enable the STALLed interrupt
(UOTGHS_DEVEPTISRx.STALLEDI).
This bit is cleared when UOTGHS_DEVEPTIDRx.STALLEDEC bit is written to one. This will disable the STALLed interrupt
(UOTGHS_DEVEPTISRx.STALLEDI).
• CRCERRE: CRC Error Interrupt
This bit is set when UOTGHS_DEVEPTIERx.CRCERRES bit is written to one. This will enable the CRC Error interrupt
(UOTGHS_DEVEPTISRx.CRCERRI).
This bit is cleared when UOTGHS_DEVEPTIDRx.CRCERREC bit is written to one. This will disable the CRC Error interrupt
(UOTGHS_DEVEPTISRx.CRCERRI).
• OVERFE: Overflow Interrupt
This bit is set when UOTGHS_DEVEPTIERx.OVERFES bit is written to one. This will enable the Overflow interrupt
(UOTGHS_DEVEPTISRx.OVERFI).
This bit is cleared when UOTGHS_DEVEPTIDRx.OVERFEC bit is written to one. This will disable the Overflow interrupt
(UOTGHS_DEVEPTISRx.OVERFI).
• NAKINE: NAKed IN Interrupt
This bit is set when UOTGHS_DEVEPTIERx.NAKINES bit is written to one. This will enable the NAKed IN interrupt
(UOTGHS_DEVEPTISRx.NAKINI).
This bit is cleared when UOTGHS_DEVEPTIDRx.NAKINEC bit is written to one. This will disable the NAKed IN interrupt
(UOTGHS_DEVEPTISRx.NAKINI).
• HBISOFLUSHE: High Bandwidth Isochronous IN Flush Interrupt
This bit is set when UOTGHS_DEVEPTIERx.HBISOFLUSHES bit is written to one. This will enable the HBISOFLUSHI
interrupt.
This bit is cleared when UOTGHS_DEVEPTIDRx.HBISOFLUSHEC bit disable the HBISOFLUSHI interrupt.
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SAM3X/A
SAM3X/A
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12