SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 409

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

25.6.2
Figure 25-3. Read Burst SDRAM Access
25.6.3
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
SDRAM Controller Read Cycle
Border Management
SDRAMC_A[12:0]
SDWE
SDCS
(Input)
SDCK
DATA
RAS
CAS
The SDRAM Controller allows burst access, incremental burst of unspecified length or single
access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus
maximizing performance of the SDRAM. If row and bank addresses do not match the previous
row/bank address, then the SDRAM controller automatically generates a precharge command,
activates the new row and starts the read command. To comply with the SDRAM timing param-
eters, additional clock cycles on SDCK are inserted between precharge and active commands
(t
uration register of the SDRAM Controller. After a read command, additional wait states are
generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the configuration
register).
For a single access or an incremented burst of unspecified length, the SDRAM Controller antici-
pates the next access. While the last value of the column is returned by the SDRAM Controller
on the bus, the SDRAM Controller anticipates the read to the next column and thus anticipates
the CAS latency. This reduces the effect of the CAS latency on the internal bus.
For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads
to the best performance. If the burst is broken (border, busy mode, etc.), the next access is han-
dled as an incrementing burst of unspecified length.
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and initi-
ates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t
mand. This is described in
RP
) and between active and read command (t
Row n
t
RCD
= 3
col a
Figure 25-4
CAS = 2
col b
Dna
below.
col c
Dnb
RCD
col d
RP
). These two parameters are set in the config-
) command and the active/read (t
Dnc
col e
Dnd
col f
Dne
Dnf
SAM3X/A
SAM3X/A
RCD
) com-
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