SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1098

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 39-24. Example of an IN Pipe with 1 Data Bank
Figure 39-25. Example of an IN Pipe with 2 Data Banks
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UOTGHS_HSTPIPIMRx.FIFOCON
UOTGHS_HSTPIPISRx.RXINI
IN
SAM3X/A
SAM3X/A
UOTGHS_HSTPIPIMRx.FIFOCON
UOTGHS_HSTPIPISRx.RXINI
(bank 0)
DATA
IN
The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze
(UOTGHS_HSTPIPIMRx.PFREEZE) field in UOTGHS_HSTPIPIMRx is zero).
The Received IN Data Interrupt (UOTGHS_HSTPIPISRx.RXINI) bit is set at the same time as
the FIFO Control (UOTGHS_HSTPIPIMRx.FIFOCON) bit when the current bank is full. This trig-
g e r s
(UOTGHS_HSTPIPIMRx.RXINE) bit is one.
UOTGHS_HSTPIPISRx.RXINI shall be cleared by software (by writing a one to the Received IN
Data Interrupt Clear bit in the Host Pipe x Clear register (UOTGHS_HSTPIPIDRx.RXINIC)) to
acknowledge the interrupt, which has no effect on the pipe FIFO.
The user then reads from the FIFO and clears the UOTGHS_HSTPIPIMRx.FIFOCON bit (by
writing a one to the FIFO Control Clear (UOTGHS_HSTPIPIDRx.FIFOCONC) bit) to free the
bank. If the IN pipe is composed of multiple banks, this also switches to the next bank. The
UOTGHS_HSTPIPISRx.RXINI and UOTGHS_HSTPIPIMRx.FIFOCON bits are updated in
accordance with the status of the next bank.
U O T G H S _ H S T P I P I S R x . R X I N I
UOTGHS_HSTPIPIMRx.FIFOCON.
The Read-write Allowed (UOTGHS_HSTPIPISRx.RWALL) bit is set when the current bank is
not empty, i.e., the software can read further data from the FIFO.
(bank 0)
DATA
a
ACK
HW
P E P _ x
SW
read data from CPU
ACK
HW
i n t e r r u p t
BANK 0
SW
read data from CPU
IN
i f
BANK 0
SW
s h a l l
t h e
IN
(bank 1)
DATA
R e c e i v e d
a l w a y s
SW
(bank 0)
DATA
b e
ACK
HW
I N
c l e a r e d
D a t a
read data from CPU
SW
ACK
HW
BANK 1
I n t e r r u p t
b e f o r e
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
read data from CPU
SW
BANK 0
c l e a r i n g
E n a b l e