SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1089

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 39-18. Abort Algorithm
39.5.2.13
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Overview
Management of OUT Endpoints
UOTGHS_DEVEPT.
UOTGHS_DEVEPTISRx.NBUSYBK
UOTGHS_DEVEPTIDRx.TXINEC =
OUT packets are sent by the host. All data which acknowledges or not the bank can be read
when it is empty.
The endpoint must be configured first.
T h e
UOTGHS_DEVEPTIMRx.FIFOCON when the current bank is full. This triggers a PEP_x inter-
rupt if the Received OUT Data Interrupt Enable (UOTGHS_DEVEPTIMRx.RXOUTE) bit is one.
UOTGHS_DEVEPTISRx.RXOUTI shall be cleared by software (by writing a one to the Received
OUT Data Interrupt Clear (UOTGHS_DEVEPTICRx.RXOUTIC) bit to acknowledge the interrupt,
which has no effect on the endpoint FIFO.
The user then reads from the FIFO and clears the UOTGHS_DEVEPTIMRx.FIFOCON bit to free
the bank. If the OUT endpoint is composed of multiple banks, this also switches to the next
bank. The UOTGHS_DEVEPTISRx.RXOUTI and UOTGHS_DEVEPTIMRx.FIFOCON bits are
updated in accordance with the status of the next bank.
U O T G H S _ D E V E P T I S R x . R X O U T I s h a l l a l w a y s b e c l e a r e d b e f o r e c l e a r i n g
UOTGHS_DEVEPTIMRx.FIFOCON.
The UOTGHS_DEVEPTISRx.RWALL bit is set when the current bank is not empty, i.e. the soft-
ware can read further data from the FIFO.
EPRSTx = 1
Abort Done
Endpoint
Abort
U O T G H S _ D E V E P T I S R x . R X O U T I
Yes
Yes
== 0?
UOTGHS_DEVEPTIERx.KILLBKS = 1
UOTGHS_DEVEPTIMRx.KILLBK == 1?
1
No
No
Disable the UOTGHS_DEVEPTISRx.TXINI interrupt.
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
Wait for the end of the
procedure
Kill the last written bank.
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