SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 791

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start
bit is detected and data, parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER to 0), a start is detected at the eighth sample to 0. Then, data
bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8
(OVER to 1), a start bit is detected at the fourth sample to 0. Then, data bits, parity bit and stop
bit are sampled on each 8 sampling clock cycle.
The number of data bits, first bit sent and parity mode are selected by the same fields and bits
as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization
mechanism only, the number of stop bits has no effect on the receiver as it considers only one
stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the
transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking
for a new start bit so that resynchronization can also be accomplished when the transmitter is
operating with one stop bit.
Figure 35-12
operates in asynchronous mode.
Figure 35-12. Asynchronous Start Detection
Figure 35-13. Asynchronous Character Reception
Clock (x16)
Baud Rate
Sampling
Sampling
Sampling
Baud Rate
Example: 8-bit, Parity Enabled
Detection
Clock
RXD
RXD
Start
Clock
RXD
and
1
1
Figure 35-13
2
2
samples
3
3
16
4
4
D0
5
5
samples
16
6
6
illustrate start detection and character reception when USART
D1
7
Detection
7
Rejection
samples
Start
Start
16
8
0
D2
1
1
samples
16
2
2
3
3
D3
samples
4
4
16
5
D4
samples
6
16
7
D5
samples
8
16
9 10 11 12 13 14 15 16
D6
samples
16
D7
samples
16
SAM3X/A
SAM3X/A
Parity
Bit
samples
16
Stop
Bit
Sampling
D0
791
791