SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 548

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

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SAM3X/A
2. Checking the Main Oscillator Frequency (Optional):
3. Setting PLL and Divider:
4. Selection of Master Clock and Processor Clock
• If a new value for CSS field corresponds to PLL Clock,
Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
The main oscillator will be enabled (MOSCXTS bit set) after 56 Slow Clock Cycles.
In some situations the user may need an accurate measure of the main clock frequency.
This measure can be accomplished via the Main Clock Frequency Register (CKGR_MCFR).
Once the MAINFRDY field is set in CKGR_MCFR, the user may read the MAINF field in
CKGR_MCFR. This provides the number of main clock cycles within sixteen slow clock
cycles.
All parameters needed to configure PLLA and the divider are located in CKGR_PLLAR.
The DIV field is used to control the divider itself. It must be set to 1 when PLL is used. By
default, DIV parameter is set to 0 which means that the divider is turned off.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0
and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is
PLL input frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before the LOCK bit is set in
PMC_SR, after CKGR_PLLAR has been written.
Once the CKGR_PLL register has been written, the user must wait for the LOCK bit to be
set in the PMC_SR. This can be done either by polling the status register or by waiting the
interrupt line to be raised if the associated interrupt to LOCK has been enabled in PMC_IER.
All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some
stage one of the following parameters, MUL or DIV is modified, the LOCK bit will go low to
indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is
constrained to wait for LOCK bit to be set before using the PLL output clock.
The Master Clock and the Processor Clock are configurable via the Master Clock Register
(PMC_MCKR).
The CSS field is used to select the Master Clock divider source. By default, the selected
clock source is main clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between
different values (1, 2, 3, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES parameter. By default, PRES parameter is set to 1 which means that master clock is
equal to main clock.
Once PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in
PMC_SR. This can be done either by polling the status register or by waiting for the interrupt
line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER
register.
The PMC_MCKR must not be programmed in a single write operation. The preferred pro-
gramming sequence for PMC_MCKR is as follows:
– Program the PRES field in PMC_MCKR.
– Wait for the MCKRDY bit to be set in PMC_SR.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12