SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 543

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

28.2.4
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Master Clock Controller
Figure 28-7. Peripheral Clock Divider Block Diagram
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLs.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR pro-
grams the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
Figure 28-8. Master Clock Controller
UPLLCK/2
MAINCK
PLLACK
SLCK
SLCK
MAINCK
PLLBCK
PLLACK
CSS
Master Clock Controller
PMC_MCKR
(PMC_MCKR)
/1,/2,/3,/4,/8,
/16,/32,/64
CSS
Prescaler
PRES
Peripherals
Control Register
(PMC_PCR)
/2, /4
Divider
PMC_MCKR
Master Clock
Prescaler
PRES
div2
div4
DIV(PID = n+1)
DIV(PID = n+2)
Sleep Mode
Processor
Controller
div2
div4
div2
div4
Clock
MCK
MCK
Processor clock c
Master clock
Peripherals
Clock Controller
(PMC_PCERx)
HCLK
int
MCK
ON/OFF
ON/OFF
ON/OFF
MCK
To the Processor
Clock C ontroller (PCK)
periph_clk[n]
periph_clk[n+1]
periph_clk[n+2]
SAM3X/A
SAM3X/A
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