SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 451

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

26.13.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
TDF Optimization Enabled (TDF_MODE = 1)
Figure 26-18. TDF Period in NCS Controlled Read Operation (TDF = 3)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the
SMC takes advantage of the setup period of the next access to optimize the number of wait
states cycle to insert.
Figure 26-19
NWE, on Chip Select 0. Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
NBS0, NBS1,
shows a read access controlled by NRD, followed by a write access controlled by
D[15:0]
A[23:2]
A0,A1
MCK
NRD
NCS
NCS controlled read operation
tpacc
TDF = 3 clock cycles
SAM3X/A
SAM3X/A
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