SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1368

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

44.6.5
44.6.6
44.6.7
1368
1368
SAM3X/A
SAM3X/A
Channel Selection
Sleep Mode
DACC Timings
In word transfer mode each time the DACC_CDR register is written 2 data items are stored in
the FIFO. The first data item sampled for conversion is DACC_CDR[15:0] and the second
DACC_CDR[31:16].
Fields DACC_CDR[15:12] and DACC_CDR[31:28] are used for channel selection if the TAG
field is set in DACC_MR register.
Warning: Writing in the DACC_CDR register while TXRDY flag is inactive will corrupt FIFO
data.
There are two means by which to select the channel to perform data conversion.
The DACC Sleep Mode maximizes power saving by automatically deactivating the DACC when
it is not being used for conversions.
When a start conversion request occurs, the DACC is automatically activated. As the analog cell
requires a start-up time, the logic waits during this time and starts the conversion on the selected
channel. When all conversion requests are complete, the DACC is deactivated until the next
request for conversion.
A fast wake-up mode is available in the
saving strategy and responsiveness. Setting the FASTW bit to 1 enables the fast wake-up
mode. In fast wake-up mode the DACC is not fully deactivated while no conversion is requested,
thereby providing less power saving but faster wake-up (4 times faster).
The DACC startup time must be defined by the user in the STARTUP field of the
Register.
This startup time differs depending of the use of the fast wake-up mode along with sleep mode,
in this case the user must set the STARTUP time corresponding to the fast wake up and not the
standard startup time.
A max speed mode is available by setting the MAXS bit to 1 in the DACC_MR register. Using
this mode, the DAC Controller no longer waits to sample the end of cycle signal coming from the
DACC block to start the next conversion and uses an internal counter instead. This mode gains
2 DACC Clock periods between each consecutive conversion.
Warning: Using this mode, the EOC interrupt of the DACC_IER register should not be used as it
is 2 DACC Clock periods late.
• By default, to select the channel where to convert the data, is to use the USER_SEL field of
• A more flexible option to select the channel for the data to be converted to is to use the tag
the
with the USER_SEL field.
mode, setting the TAG field of the
DACC_CDR[13:12] which are otherwise unused, are employed to select the channel in the
same way as with the USER_SEL field. Finally, if the WORD field is set, the 2 bits,
DACC_CDR[13:12] are used for channel selection of the first data and the 2 bits,
DACC_CDR[29:28] for channel selection of the second data.
DACC Mode
Register. Data requests will merely be converted to the channel selected
DACC Mode Register
DACC Mode Register
to 1. In this mode the 2 bits,
as a compromise between power
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
DACC Mode