SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 93

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11.11.4
11.11.4.1
11.11.4.2
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Shift Operations
ASR
LSR
Register shift operations move the bits in a register left or right by a specified number of bits, the
shift length. Register shift can be performed:
The permitted shift lengths depend on the shift type and the instruction, see the individual
instruction description or
occurs. Register shift operations update the carry flag except when the specified shift length is 0.
The following sub-sections describe the various shift operations and how they affect the carry
flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift
length.
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register
into the left-hand n bits of the result. See
You can use the ASR #n operation to divide the value in the register Rm by 2
being rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Figure 11-4. ASR #3
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n
places, into the right-hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0.
See
You can use the LSR #n operation to divide the value in the register Rm by 2
regarded as an unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS,
MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
• directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a
• during the calculation of Operand2 by the instructions that specify the second operand as a
• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
• If n is 32 or more, then all the bits in the result are cleared to 0.
destination register
register with shift, see
instruction.
Figure
31
11-5.
“Flexible second operand” on page
“Flexible second operand” on page
...
Figure 11-4 on page
91. The result is used by the
91. If the shift length is 0, no shift
93.
5
4
3
2
1 0
SAM3X/A
SAM3X/A
n
n
, with the result
Carry
, if the value is
Flag
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