SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 953

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

37.14.2
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• CLKDIV: Clock Divider
High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
• PWSDIV: Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2
Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN
bit).
• RDPROOF Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0: Disables Read Proof.
1: Enables Read Proof.
• WRPROOF Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
0: Disables Write Proof.
1: Enables Write Proof.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
0: Disables Force Byte Transfer.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
31
23
15
–
7
HSMCI Mode Register
HSMCI_MR
0x40000004
Read-write
PADV
30
22
14
6
FBYTE
29
21
13
5
WRPROOF
28
20
12
4
BLKLEN
BLKLEN
CLKDIV
(PWSDIV)
“HSMCI Write Protect Mode Register” on page
RDPROOF
+ 1 when entering Power Saving Mode.
27
19
11
3
26
18
10
2
PWSDIV
25
17
9
1
SAM3X/A
SAM3X/A
978.
24
16
8
0
953
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