SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 71

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11.5.4.2
11.5.4.3
11.5.5
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Bit-banding
DSB
ISB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transac-
tions complete before subsequent instructions execute. See
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory
transactions is recognizable by subsequent instructions. See
Use memory barrier instructions in, for example:
Memory accesses to Strongly-ordered memory, such as the system control block, do not require
the use of DMB instructions.
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1MB of the SRAM and peripheral memory regions.
The memory map has two 32MB alias regions that map to two 1MB bit-band regions:
• MPU programming:
• Vector table. If the program changes an entry in the vector table, and then enables the
• Self-modifying code. If a program contains self-modifying code, use an ISB instruction
• Memory map switching. If the system contains a memory map switching mechanism, use a
• Dynamic exception priority change. When an exception priority has to change when the
• Using a semaphore in multi-master system. If the system contains more than one bus
• accesses to the 32MB SRAM alias region map to the 1MB SRAM bit-band region, as shown
corresponding exception, use a DMB instruction between the operations. This ensures that if
the exception is taken immediately after being enabled the processor uses the new exception
vector.
immediately after the code modification in the program. This ensures subsequent instruction
execution uses the updated program.
DSB instruction after switching the memory map in the program. This ensures subsequent
instruction execution uses the updated memory map.
exception is pending or active, use DSB instructions after the change. This ensures the
change takes effect on completion of the DSB instruction.
master, for example, if another processor is present in the system, each processor must use
a DMB instruction after any semaphore instructions, to ensure other bus masters see the
memory transactions in the order in which they were executed.
in
– Use a DSB instruction to ensure the effect of the MPU takes place immediately at
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
Table 11-6
the end of context switching.
programming the MPU region or regions, if the MPU configuration code was
accessed using a branch or call. If the MPU configuration code is entered using
exception mechanisms, then an ISB instruction is not required.
“DSB” on page
“ISB” on page
146.
145.
SAM3X/A
SAM3X/A
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