SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 449

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

26.12.3.1
26.12.3.2
26.12.4
26.13 Data Float Wait States
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Read to Write Wait State
User Procedure
Slow Clock Mode Transition
When detecting that a new user configuration has been written in the user interface, the SMC
inserts a wait state before starting the next access. The so called “Reload User Configuration
Wait State” is used by the SMC to load the new set of parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If
accesses before and after re-programming the user interface are made to different devices
(Chip Selects), then one single Chip Select Wait State is applied.
On the other hand, if accesses before and after writing the user interface are made to the same
device, a Reload Configuration Wait State is inserted, even if the change does not concern the
current Chip Select.
To insert a Reload Configuration Wait State, the SMC detects a write access to any
SMC_MODE register of the user interface. If only the timing registers are modified
(SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, the user must vali-
date the modification by writing the SMC_MODE register, even if no change was made on the
mode parameters.
A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or
exited, after the end of the current transfer (see
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and
write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states
when they are to be inserted. See
Some memory devices are slow to release the external bus. For such devices, it is necessary to
add wait states (data float wait states) after a read access:
The Data Float Output Time (t
TDF_CYCLES field of the SMC_MODE register for the corresponding chip select. The value of
TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the
external device releases the bus, and represents the time allowed for the data output to go to
high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long t
memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE
fields of the SMC_MODE register for the corresponding chip select.
• before starting a read access to a different external memory,
• before starting a write access to the same device or to a different external one.
DF
will not slow down the execution of a program from internal
DF
Figure 26-13 on page
) for each external memory device is programmed in the
“Slow Clock Mode” on page
446.
460).
SAM3X/A
SAM3X/A
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