SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 398

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

24.7.1
24.7.2
24.7.3
24.7.4
24.7.5
24.8
24.8.1
24.8.1.1
398
398
Implementation Examples
SAM3X/A
SAM3X/A
Bus Multiplexing
Static Memory Controller
Nand Flash Controller
SDRAM Controller
ECC Controller
SDR-SDRAM
Software Configuration
The external memory bus offers a complete set of control signals that share the 16-bit data lines,
the address lines of up to 24 bits and the control signals through a multiplex logic operating in
function of the memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAM Controller without
delaying the other external Memory Controller accesses.
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
For information on the Nand Flash Controller, refer to the Static Memory Controller Section.
For information on the SDRAM Controller, refer to the SDRAMC Section.
For information on the ECC Controller, refer to the Static Memory Controller Section.
Figure 24-2. 2 x 8-bit SDR-SDRAM Hardware Configuration
The following configuration must be respected:
• The ECC Controller (ECC)
Controller
SDRAM
A[2-11 ], A13
D0-D15
SDCKE
SDCS
SDCK
SDWE
NBS0
NBS1
RAS
CAS
BA0
BA1
D0-D7
SDWE
NBS0
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
2M x 8
A0-A9, A11
BA0
BA1
A10 SDA10
A[2-11 ], A13
BA0
BA1
D8-D15
SDWE
NBS1
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
2M x 8
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
A0-A9, A11
BA0
BA1
A10
A[2-11 ], A13
SDA10
BA0
BA1