SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 412

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 25-6. Self-refresh Mode Behavior
25.6.5.2
412
412
SDRAMC_A[12:0]
SDRAMC_SRR
SDCKE
SDWE
SDCK
SDCS
SAM3X/A
SAM3X/A
Write
RAS
CAS
Low-power Mode
SRCB = 1
and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to
the low-power SDRAM during initialization.
After initialization, as soon as PASR/DS/TCSR fields are modified and self-refresh mode is acti-
vated, the Extended Mode Register is accessed automatically and PASR/DS/TCSR bits are
updated before entry into self-refresh mode. This feature is not supported when SDRAMC
shares an external bus with another controller.
The SDRAM device must remain in self-refresh mode for a minimum period of t
remain in self-refresh mode for an indefinite period. This is described in
This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register.
Power consumption is greater than in self-refresh mode. All the input and output buffers of the
SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms for a whole device refresh operation). As no auto-refresh operations are performed by the
SDRAM itself, the SDRAM Controller carries out the refresh operation. The exit procedure is
faster than in self-refresh mode.
This is described in
Figure
25-7.
Self Refresh Mode
to the SDRAM Controller
Access Request
T
Figure
XSR
= 3
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
25-6.
RAS
Row
and may