SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 691
SAM3X8E
Manufacturer Part Number
SAM3X8E
Description
Manufacturer
Atmel Corporation
- Current page: 691 of 1465
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Figure 32-10. Peripheral Deselection
32.7.3.10
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Write SPI_TDR
Write SPI_TDR
Write SPI_TDR
Write SPI_TDR
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
TDRE
TDRE
TDRE
TDRE
Mode Fault Detection
PCS = A
A
A
A
A
CSAAT = 0 and CSNAAT = 0
CSAAT = 0 and CSNAAT = 0
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS signal. In this case, multi-master configuration,
NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO control-
ler). When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read
DLYBCT
DLYBCT
DLYBCT
DLYBCT
DLYBCS
DLYBCS
DLYBCS
PCS = B
PCS=A
A
PCS = A
A
B
A
PCS = A
A
A
A
A
CSAAT = 0 and CSNAAT = 1
CSAAT = 1 and CSNAAT= 0 / 1
DLYBCT
DLYBCT
DLYBCT
DLYBCT
DLYBCS
DLYBCS
PCS = B
PCS = A
DLYBCS
A
A
PCS = A
DLYBCS
SAM3X/A
SAM3X/A
A
A
A
B
691
691
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