SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 171

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11.21.5
• TBLOFF
Vector table base offset field. It contains bits[29:7] of the offset of the table base from the bottom of the memory map.
Bit[29] determines whether the vector table is in the code or SRAM memory region:
0: code
1: SRAM.
Bit[29] is sometimes called the TBLBASE bit.
When setting TBLOFF, you must align the offset to the number of exception entries in the vector table. The minimum align-
ment is 32 words, enough for up to 16 interrupts. For more interrupts, adjust the alignment by rounding up to the next power
of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because the required table
size is 37 words, and the next power of two is 64.
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
TBLOFF
31
23
15
7
Vector Table Offset Register
Reserved
30
22
14
6
The VTOR indicates the offset of the vector table base address from memory address
0x00000000. See the register summary in
The bit assignments are:
29
21
13
5
28
20
12
4
TBLOFF
TBLOFF
Reserved
27
19
11
3
Table 11-30 on page 165
TBLOFF
26
18
10
2
for its attributes.
25
17
9
1
SAM3X/A
SAM3X/A
24
16
8
0
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