SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1101

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

39.5.4
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Pipe interrupts
DMA interrupts
USB DMA Operation
There is no exception host global interrupt.
The processing host pipe interrupts are:
The exception host pipe interrupts are:
The processing host DMA interrupts are:
There is no exception host DMA interrupt.
USB packets of any length may be transferred when required by the UOTGHS. These transfers
always feature sequential addressing. These two characteristics mean that in case of high UOT-
GHS throughput, both AHB ports will benefit from “incrementing burst of unspecified length”
since the average access latency of AHB slaves can then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data
transfers and channel descriptor loading. A burst may last on the AHB busses for the duration of
a whole USB packet transfer, unless otherwise broken by the AHB arbitration or the AHB
1 kbyte boundary crossing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus band-
width performance boost with paged memories. This is because these memory row (or bank)
changes, which are very clock-cycle consuming, will then likely not occur or occur once instead
of dozens of times during a single big USB packet DMA transfer in case other AHB masters
address the memory. This means up to 128 words single cycle unbroken AHB bursts for bulk
pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints.
This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size
• The Host Start of Frame Interrupt (UOTGHS_HSTISR.HSOFI)
• The Host Wake-Up Interrupt (UOTGHS_HSTISR.HWUPI)
• The Pipe x Interrupt (UOTGHS_HSTISR.PEP_x)
• The DMA Channel x Interrupt (UOTGHS_HSTISR.DMAxINT)
• The Received IN Data Interrupt (UOTGHS_HSTPIPISRx.RXINI)
• The Transmitted OUT Data Interrupt (UOTGHS_HSTPIPISRx.TXOUTI)
• The Transmitted SETUP Interrupt (UOTGHS_HSTPIPISRx.TXSTPI)
• The Short Packet Interrupt (UOTGHS_HSTPIPISRx.SHORTPACKETI)
• The Number of Busy Banks (UOTGHS_HSTPIPISRx.NBUSYBK) interrupt
• The Underflow Interrupt (UOTGHS_HSTPIPISRx.UNDERFI)
• The Pipe Error Interrupt (UOTGHS_HSTPIPISRx.PERRI)
• The NAKed Interrupt (UOTGHS_HSTPIPISRx.NAKEDI)
• The Overflow Interrupt (UOTGHS_HSTPIPISRx.OVERFI)
• The Received STALLed Interrupt (UOTGHS_HSTPIPISRx.RXSTALLDI)
• The CRC Error Interrupt (UOTGHS_HSTPIPISRx.CRCERRI)
• The End of USB Transfer Status (UOTGHS_HSTDMASTATUSx.END_TR_ST) interrupt
• The End of Channel Buffer Status (UOTGHS_HSTDMASTATUSx.END_BF_ST) interrupt
• The Descriptor Loaded Status (UOTGHS_HSTDMASTATUSx.DESC_LDST) interrupt
SAM3X/A
SAM3X/A
1101
1101