SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 645

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 31-4. Output Line Timings
31.5.8
31.5.9
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Write PIO_CODR
Write PIO_SODR
Inputs
Input Glitch and Debouncing Filters
PIO_ODSR
PIO_PDSR
MCK
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the
debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow
Clock.
The selection between glitch filtering or debounce filtering is done by writing in the registers
PIO_SCIFSR (System Clock Glitch Input Filter Select Register) and PIO_DIFSR (Debouncing
Input Filter Select Register). Writing PIO_SCIFSR and PIO_DIFSR respectively, sets and clears
bits in PIO_IFDGSR.
The current selection status can be checked by reading the register PIO_IFDGSR (Glitch or
Debouncing Input Filter Selection Status Register).
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV
field of the PIO_SCDR (Slow Clock Divider Register)
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2
Selected Clock Cycle (Selected Clock represents MCK or Divided Slow Clock depending on
PIO_SCIFSR and PIO_DIFSR programming) is automatically rejected, while a pulse with a
duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is accepted. For pulse
durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may
• If PIO_IFDGSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period
• If PIO_IFDGSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2
of Master Clock.
Period of the Programmable Divided Slow Clock.
APB Access
2 cycles
APB Access
2 cycles
SAM3X/A
SAM3X/A
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