SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 797

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

35.7.3.9
35.7.3.10
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Multidrop Mode
Transmitter Timeguard
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status
Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with
the RSTSTA bit to 1.
Figure 35-22. Parity Error
If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the
USART runs in Multidrop Mode. This mode differentiates the data characters and the address
characters. Data is transmitted with the parity bit to 0 and addresses are transmitted with the
parity bit to 1.
If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when
the parity bit is high and the transmitter is able to send a character with the parity bit high when
the Control Register is written with the SENDA bit to 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit
RSTSTA to 1.
The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this
case, the next byte written to US_THR is transmitted as an address. Any character written in
US_THR without having written the command SENDA is transmitted normally with the parity to
0.
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between
two characters. This idle state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Regis-
ter (US_TTGR). When this field is programmed to zero no timeguard is generated. Otherwise,
the transmitter holds a high level on TXD after each transmitted byte during the number of bit
periods programmed in TG in addition to the number of stop bits.
As illustrated in
the programming of a timeguard. TXRDY rises only when the start bit of the next character is
sent, and thus remains to 0 during the timeguard transmission if a character has been written in
Baud Rate
RXRDY
US_CR
PARE
Clock
Write
Figure
RXD
Figure 35-22
35-23, the behavior of TXRDY and TXEMPTY status bits is modified by
Start
Bit
D0
D1
illustrates the parity bit status setting and clearing.
D2
D3
D4
D5
D6
D7
Parity
Bad
Bit
Stop
Bit
RSTSTA = 1
SAM3X/A
SAM3X/A
797
797