SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 408

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

25.5.4
25.6
25.6.1
Figure 25-2. Write Burst SDRAM Access
408
408
SDRAMC_A[12:0]
SDWE
SDCS
SDCK
DATA
Functional Description
RAS
CAS
SAM3X/A
SAM3X/A
Power Management
SDRAM Controller Write Cycle
Row n
The SDRAM Controller may be clocked through the Power Management Controller (PMC), thus
the programmer must first configure the PMC to enable the SDRAM Controller clock. The
SDRAM Controller Clock (not the SDCK pin) is managed by the Static Memory Controller Clock.
The SDRAM Clock on SDCK pin will be output as soon as the first access to the SDRAM is done
during the initialization phase.
If one needs to stop the SDRAM clock signal, the Low Power Mode Register (SDRAMC_LPR)
must be programmed with the sefl-refresh command.
The SDRAM Controller allows burst access or single access. In both cases, the SDRAM control-
ler keeps track of the active row in each bank, thus maximizing performance. To initiate a burst
access, the SDRAM Controller uses the transfer type signal provided by the master requesting
the access. If the next access is a sequential write access, writing to the SDRAM device is car-
ried out. If the next access is a write-sequential access, but the current access is to a boundary
page, or if the next access is in another row, then the SDRAM Controller generates a precharge
command, activates the new row and initiates a write command. To comply with SDRAM timing
parameters, additional clock cycles are inserted between precharge/active (t
active/write (t
Configuration Register” on page
t
RCD
= 3
col a
RCD
Dna
) commands. For definition of these timing parameters, refer to the
col b
Dnb
col c
Dnc
418. This is described in
col d
Dnd
col e
Dne
col f
Dnf
col g
Dng
Figure 25-2
col h
Dnh
col i
Dni
below.
col j
Dnj
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
RP
) commands and
col k
Dnk
“SDRAMC
col l
Dnl