SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 646

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 31-5. Input Glitch Filter Timing
Figure 31-6. Input Debouncing Filter Timing
31.5.10
646
646
Divided Slow Clock
if PIO_IFSR = 0
if PIO_IFSR = 1
PIO_PDSR
PIO_PDSR
Pin Level
SAM3X/A
SAM3X/A
if PIO_IFSR = 0
if PIO_IFSR = 1
Input Edge/Level Interrupt
PIO_PDSR
PIO_PDSR
Pin Level
MCK
up to 2 cycles Tmck
not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to
be visible it must exceed 1 Selected Clock cycle, whereas for a glitch to be reliably filtered out,
its duration must not exceed 1/2 Selected Clock cycle.
The filters also introduce some latencies, this is illustrated in
The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs
on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt
detection. The glitch and debouncing filters require that the PIO Controller clock is enabled.
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a
level on an I/O line. The Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt
Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and dis-
able the input change interrupt by setting and clearing the corresponding bit in PIO_IMR
(Interrupt Mask Register). As Input change detection is possible only by comparing two succes-
1 cycle
1 cycle
up to 2 cycles Tmck
PIO_IFCSR = 1
PIO_IFCSR = 0
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 1.5 cycles
1 cycle
up to 2.5 cycles
up to 2 cycles Tmck
2 cycles
Figure 31-5
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles
and
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
1 cycle
1 cycle
Figure
up to 2 cycles Tmck
31-6.