SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 80

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11.6.5
11.6.6
11.6.7
11.6.7.1
80
80
SAM3X/A
SAM3X/A
Exception priorities
Interrupt priority grouping
Exception entry and return
Preemption
As
If software does not configure any priorities, then all exceptions with a configurable priority have
a priority of 0. For information about configuring exception priorities see
Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and
NMI exceptions, with fixed negative priority values, always have higher priority than any other
exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1]
means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1]
is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest
exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and
have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception
being handled, the handler is not preempted, irrespective of the exception number. However,
the status of the new interrupt changes to pending.
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
divides each interrupt priority register entry into two fields:
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler,
If multiple pending interrupts have the same group priority, the subpriority field determines the
order in which they are processed. If multiple pending interrupts have the same group priority
and subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
“Application Interrupt and Reset Control Register” on page
Descriptions of exception handling use the following terms:
When the processor is executing an exception handler, an exception can preempt the exception
handler if its priority is higher than the priority of the exception being handled. See
ority grouping” on page 80
• a lower priority value indicating a higher priority
• configurable priorities for all exceptions except Reset, Hard fault.
•
•
• an upper field that defines the group priority
• a lower field that defines a subpriority within the group.
Table 11-9 on page 77
“System Handler Priority Registers” on page 176
“Interrupt Priority Registers” on page
shows, all exceptions have an associated priority, with:
for more information about preemption by an interrupt.
160.
172.
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11057A–ATARM–17-Feb-12
“Interrupt pri-