SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1145

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

• FIFOCON: FIFO Control
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When
read, their value is always 0.
For IN endpoints:
For OUT endpoints:
• KILLBK: Kill IN Bank
This bit is set when UOTGHS_DEVEPTIERx.KILLBKS bit is written to one. This will kill the last written bank.
This bit is cleared when the bank is killed.
Caution: The bank is really cleared when the “kill packet” procedure is accepted by the UOTGHS core. This bit is automat-
ically cleared after the end of the procedure:
The bank is really killed: UOTGHS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared but sent (IN transfer): UOTGHS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared because it was empty.
The user shall wait for this bit to be cleared before trying to kill another packet.
This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent on the
USB line. If at least 2 banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. Indeed,
in this case, the current bank is sent (IN transfer) while the last bank is killed.
• NBUSYBKE: Number of Busy Banks Interrupt
This bit is set when UOTGHS_DEVEPTIERx.NBUSYBKES bit is written to one. This will enable the Number of Busy Banks
interrupt (UOTGHS_DEVEPTISRx.NBUSYBK).
This bit is cleared when UOTGHS_DEVEPTIDRx.NBUSYBKEC bit is written to zero. This will disable the Number of Busy
Banks interrupt (UOTGHS_DEVEPTISRx.NBUSYBK).
• ERRORTRANSE: Transaction Error Interrupt
This bit is set when UOTGHS_DEVEPTIERx.ERRORTRANSES bit is written to one. This will enable the transaction error
interrupt (UOTGHS_DEVEPTISRx.ERRORTRANS).
This bit is cleared when UOTGHS_DEVEPTIDRx.ERRORTRANSEC bit is written to one. This will disable the transaction
error interrupt (UOTGHS_DEVEPTISRx.ERRORTRANS).
• DATAXE: DataX Interrupt
This bit is set when UOTGHS_DEVEPTIERx.DATAXES bit is written to one. This will enable the DATAX interrupt. (see
DTSEQ bits)
This bit is cleared when UOTGHS_DEVEPTIDRx.DATAXEC bit is written to one. This will disable the DATAX interrupt.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
This bit is set when the current bank is free, at the same time as UOTGHS_DEVEPTISRx.TXINI.
This bit is cleared (by writing a one to UOTGHS_DEVEPTIDRx.FIFOCONC bit) to send the FIFO data and to switch to
the next bank.
This bit is set when the current bank is full, at the same time as UOTGHS_DEVEPTISRx.RXOUTI.
This bit is cleared (by writing a one to UOTGHS_DEVEPTIDRx.FIFOCONC bit) to free the current bank and to switch
to the next bank.
SAM3X/A
SAM3X/A
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