SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 365

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Figure 23-9. DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address
23.4.6
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Disabling a Channel Prior to Transfer Completion
Under normal operation, the software enables a channel by writing a ‘1’ to the Channel Handler
Enable Register, DMAC_CHER.ENAx, and the hardware disables a channel on transfer comple-
tion by clearing the DMAC_CHSR.ENAx register bit.
The recommended way for software to disable a channel without losing data is to use the
SUSPx bit in conjunction with the EMPTx bit in the Channel Handler Status Register.
Completed Interrupt generated here
DMAC Chained Buffer Transfer
Buffer Transfer Completed
Interrupt generated here
SADDRx, CTRLAx,CTRLBx, DSCRx
Hardware reprograms
DMAC buffer transfer
Channel enabled by
Writeback of control
Channel disabled by
information of LLI
Is DMAC in
LLI Fetch
Row 1 ?
software
hardware
yes
no
SAM3X/A
SAM3X/A
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