SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 334

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

22.5.1.1
22.5.1.2
22.5.2
22.5.2.1
22.5.2.2
334
334
SAM3X/A
SAM3X/A
Round-Robin Arbitration
Undefined Length Burst Arbitration
Slot Cycle Limit Arbitration
Round-Robin arbitration without default master
Round-Robin arbitration with last access master
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix
provides specific logic in order to re-arbitrate before the end of the INCR transfer.
A predicted end of burst is used as for defined length burst transfer, which is selected between
the following:
This selection can be done through the ULBT field of the Master Configuration Registers
(MATRIX_MCFG).
The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a
very slow slave (e.g. an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter
reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or
word transfer.
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave in a round-robin manner. If two or more master’s requests arise at the same
time, the master with the lowest number is first serviced then the others are serviced in a round-
robin manner.
There are three round-robin algorithm implemented:
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch
requests from different masters to the same slave in a pure round-robin manner. At the end of
the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency cycle for the first access of a burst. Arbitration without
default master can be used for masters that perform significant bursts.
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to
remove the one latency cycle for the last master that accessed the slave. In fact, at the end of
the current transfer, if no other master request is pending, the slave remains connected to the
last master that performs the access. Other non privileged masters will still get one latency cycle
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will
2. Four beat bursts: predicted end of burst is generated at the end of each four beat
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat
• Round-Robin arbitration without default master
• Round-Robin arbitration with last access master
• Round-Robin arbitration with fixed default master
never be broken.
boundary inside INCR transfer.
boundary inside INCR transfer.
boundary inside INCR transfer.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12