SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 889

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

36.6.14.5
36.6.15
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
2-bit Gray Up/Down Counter for Stepper Motor
Speed Measurement
In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on
the TC_CV0 register.
Therefore, the accurate position can be read on both TC_CV registers and concatenated to form
a 32-bit word.
The timer/counter channel 0 is cleared for each increment of IDX count value.
Depending on the quadrature signals, the direction is decoded and allows to count up or down in
timer/counter channels 0 and 1. The direction status is reported on TC_QISR register.
When SPEEDEN is set in TC_BMR register, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2
must be configured in waveform mode (WAVE bit field set) in TC_CMR2 register. WAVSEL bit
field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC
value. ACPC field must be defined at 0x11 to toggle TIOA output.
This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are
set.
Channel 0 must be configured in capture mode (WAVE = 0 in TC_CMR0). ABETRG bit field of
TC_CMR0 must be configured at 1 to get TIOA as a trigger for this channel.
EDGTRG can be set to 0x01, to clear the counter on a rising edge of the TIOA signal and LDRA
field must be set accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared
(LDRB must be set to 0x01). As a consequence, at the end of each time base period the differ-
entiation required for the speed calculation is performed.
The process must be started by configuring the TC_CR register with CLKEN and SWTRG.
The speed can be read on TC_RA0 register in TC_CMR0.
Channel 1 can still be used to count the number of revolutions of the motor.
Each channel can be independently configured to generate a 2-bit gray count waveform on cor-
responding TIOA,TIOB outputs by means of GCEN bit in TC_SMMRx registers.
Up or Down count can be defined by writing bit DOWN in TC_SMMRx registers.
It is mandatory to configure the channel in WAVE mode in TC_CMR register.
The period of the counters can be programmed on TC_RCx registers.
SAM3X/A
SAM3X/A
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