SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 355

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

23.4.4.2
23.4.4.3
23.4.5
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Contiguous Address Between Buffers
Suspension of Transfers Between Buffers
Programming a Channel
Programming DMAC for Multiple Buffer Transfers
Ending Multi-buffer Transfers
Table 23-4.
Notes:
In this case, the address between successive buffers is selected to be a continuation from the
end of the previous buffer. Enabling the source or destination address to be contiguous between
buffers is a function of DMAC_CTRLAx.SRC_DSCR and DMAC_CTRLAx.DST_DSCR
registers.
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
Note:
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
All multi-buffer transfers must end as shown in Row 1 of
every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer
descriptor in memory so that LLI.DMAC_CTRLBx.SRC_DSCR is set to 0.
Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and
DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take
place, and which type of multi-buffer transfer is used. The different transfer types are shown in
Table 23-4 on page
2) Multi Buffer transfer with
3) Multi Buffer transfer with
4) Multi Buffer transfer with
buffer of a multiple buffer
• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTCx = ‘1’, where x is the channel
• the channel end of the Chained Buffer Transfer Completed Interrupt is unmasked,
1) Single Buffer or Last
number.
DMAC_EBCIMR.CBTCx = ‘1’, when n is the channel number.
contiguous DADDR
contiguous SADDR
Transfer Type
LLI support
1. USR means that the register field is manually programmed by the user.
2. CONT means that address are contiguous.
3. Channel stalled is true if the relevant BTC interrupt is not masked.
4. LLI means that the register field is updated with the content of the linked list item.
The Buffer Transfer Completed Interrupt is generated at the completion of the buffer transfer to the
destination.
transfer
Multiple Buffers Transfer Management
355.
SRC_DSCR
–
0
1
0
DST_DSCR
–
1
0
0
BTSIZE
USR
LLI
LLI
LLI
DSCR
Table 23-4 on page
USR
USR
USR
0
SADDR
CONT
USR
LLI
LLI
DADDR Other Fields
CONT
USR
LLI
LLI
355. At the end of
SAM3X/A
SAM3X/A
USR
LLI
LLI
LLI
355
355