SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 154

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

154
154
SAM3X/A
SAM3X/A
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Regis-
ters. For more information see the description of the NVIC_SetPriority function in
programming hints” on page
onto the interrupt registers and corresponding CMSIS variables that have one bit per interrupt.
Table 11-28. Mapping of interrupts to the interrupt variables
1.
Interrupts
0-29
30-63
• the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the
array IP[0] to IP[29] corresponds to the registers IPR0-IPR7, and the array entry IP[n] holds
the interrupt priority for interrupt n.
Each array element corresponds to a single NVIC register, for example the element
ICER[0] corresponds to the ICER0 register.
CMSIS array elements
Set-enable
ISER[0]
ISER[1]
Clear-enable
ICER[0]
ICER[1]
164.
Table 11-28
(1)
Set-pending
ISPR[0]
ISPR[1]
shows how the interrupts, or IRQ numbers, map
Clear-pending
ICPR[0]
ICPR[1]
Active Bit
IABR[0]
IABR[1]
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
“NVIC